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| VND5050AJ-E VND5050AK-E Double channel high side driver with analog current sense for automotive applications Features Max transient supply voltage Operating voltage range Max On-State resistance (per ch.) Current limitation (typ) Off state supply current 1. Typical value with all loads connected VCC RON ILIMH IS 41V VCC 4.5 to 36V 50 m 18 A 2 A(1) PowerSSO-12 PowerSSO-24 Application Main - Inrush current active management by power limitation - Very low stand-by current - 3.0V CMOS compatible input - Optimized electromagnetic emission - Very low electromagnetic susceptibility - In compliance with the 2002/95/ec european directive Diagnostic Functions - Proportional load current sense - High current sense precision for wide range currents - Current sense disable - Thermal shutdown indication - Very low current sense leakage Protections - Undervoltage shut-down - Overvoltage clamp - Load current limitation - Self limiting of fast thermal transients - Protection against loss of ground and loss of VCC - Thermal shut down - Reverse battery protection (see Application schematic) - Electrostatic discharge protection All types of resistive, inductive and capacitive loads Suitable as LED driver Description The VND5050AJ-E, VND5050AK-E is a monolithic device made using STMicroelectronics VIPower M0-5 technology. It is intended for driving resistive or inductive loads with one side connected to ground. Active VCC pin voltage clamp protects the device against low energy spikes (see ISO7637 transient compatibility table). This device integrates an analog current sense which delivers a current proportional to the load current (according to a known ratio) when CS_DIS is driven low or left open. When CS_DIS is driven high, the current sense pin is in a high impedance condition. Output current limitation protects the device in overload condition. In case of long overload duration, the device limits the dissipated power to safe level up to thermal shut-down intervention. Thermal shut-down with automatic restart allows the device to recover normal operation as soon as fault condition disappears. February 2008 Rev 7 1/38 www.st.com 38 Contents VND5050AJ-E / VND5050AK-E Contents 1 2 Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1 2.2 2.3 2.4 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.1 GND protection network against reverse battery . . . . . . . . . . . . . . . . . . . 21 3.1.1 3.1.2 Solution 1 : resistor in the ground line (RGND only) . . . . . . . . . . . . . . . 21 Solution 2 : diode (DGND) in the ground line . . . . . . . . . . . . . . . . . . . . 22 3.2 3.3 3.4 Load dump protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 MCU I/Os protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Maximum demagnetization energy (VCC = 13.5V) . . . . . . . . . . . . . . . . . 23 4 Package and PCB thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.1 4.2 PowerSSO-12TM thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 PowerSSO-24TM thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5 Package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5.1 5.2 5.3 5.4 5.5 ECOPACK(R) packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 PowerSSO-12TM package information . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 PowerSSO-24TM package information . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 PowerSSO-12TM packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 PowerSSO-24TM packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 6 7 Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 2/38 VND5050AJ-E / VND5050AK-E List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 8. Table 7. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Pin function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Suggested connections for unused and N.C. pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Power section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Switching (VCC = 13V; Tj = 25C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Protections and diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Logic input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Current sense (8V List of figure VND5050AJ-E / VND5050AK-E List of figure Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. Figure 41. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Configuration diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Current and voltage conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Current sense delay characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Delay response time between rising edge of ouput current and rising edge of current sense (CS enabled) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 IOUT/ISENSE Vs. IOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Maximum current sense ratio drift vs load current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Output voltage drop limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Off state output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 High level input current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Input clamp voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Input high level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Input low level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Input hysteresis voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 On state resistance Vs. Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 On state resistance Vs. VCC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Undervoltage shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 ILIMH Vs. Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Turn-On voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Turn-Off voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 STAT_DIS clamp voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Low level STAT_DIS voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 High level STAT_DIS voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Maximum turn Off current versus inductance (for each channel) . . . . . . . . . . . . . . . . . . . . 23 PowerSSO-12TM PC board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Rthj-amb Vs. PCB copper area in open box free air condition (one channel ON) . . . . . . . 24 PowerSSO-12TM thermal impedance junction ambient single pulse (one channel ON) . . . 25 Thermal fitting model of a double channel HSD in PowerSSO-12TM . . . . . . . . . . . . . . . . . 25 PowerSSO-24TM PC board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Rthj-amb Vs. PCB copper area in open box free air condition (one channel ON) . . . . . . . 27 PowerSSO-24TM Thermal impedance junction ambient single pulse (one channel ON) . . 28 Thermal fitting model of a double channel HSD in PowerSSO-24TM . . . . . . . . . . . . . . . . . 28 PowerSSO-12TM package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 PowerSSO-24TM package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 PowerSSO-12TM tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 PowerSSO-12TM tape and reel shipment (suffix "TR") . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 PowerSS0-24TM tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 PowerSSO-24TM tape and reel shipment (suffix "TR") . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 4/38 VND5050AJ-E / VND5050AK-E Block diagram and pin description 1 Block diagram and pin description Figure 1. Block diagram VCC VCC CLAMP GND INPUT1 LOGIC UNDERVOLTAGE OUTPUT1 PwCLAMP 1 DRIVER 1 ILIM 1 PwrLIM 1 VDSLIM 1 OVERTEMP. 1 DRIVER 2 ILIM 2 VDSLIM 2 OVERTEMP. 2 IOUT2 PwrLIM 2 K2 PwCLAMP 2 OUTPUT2 CURRENT SENSE2 CURRENT SENSE1 INPUT2 IOUT1 K1 CS_DIS Table 1. Name VCC OUTPUT1,2 GND INPUT1,2 CURRENT SENSE1,2 CS_DIS Pin function Function Battery connection. Power output. Ground connection. Must be reverse battery protected by an external diode/resistor network. Voltage controlled input pin with hysteresis, CMOS compatible. Controls output switch state. Analog current sense pin, delivers a current proportional to the load current Active high CMOS compatible pin, to disable the current sense pin. 5/38 Block diagram and pin description Figure 2. Configuration diagram (top view) TAB = Vcc GND INPUT2 INPUT1 CURRENT SENSE1 CURRENT SENSE2 CS_DIS 1 2 3 4 5 6 12 11 10 9 8 7 Vcc OUTPUT2 OUTPUT2 OUTPUT1 OUTPUT1 Vcc VCC GND N.C. INPUT2 N.C. INPUT1 N.C. CURRENT SENSE1 N.C. CURRENT SENSE2 CS_DIS. VCC VND5050AJ-E / VND5050AK-E OUTPUT2 OUTPUT2 OUTPUT2 OUTPUT2 OUTPUT2 OUTPUT2 OUTPUT1 OUTPUT1 OUTPUT1 OUTPUT1 OUTPUT1 OUTPUT1 TAB = VCC PowerSSO-12 PowerSSO-24 Table 2. Suggested connections for unused and N.C. pins Current Sense N.R.(1) Through 1K resistor N.C. X X Output X N.R.(1) Input X Through 10K resistor CS_DIS X Through 10K resistor Connection / pin Floating To ground 1. Not recommended. 6/38 VND5050AJ-E / VND5050AK-E Electrical specifications 2 Electrical specifications Figure 3. Current and voltage conventions IS VCC VFn ICSD VCSD IIN1 VIN1 IIN2 VIN2 INPUT2 GND CURRENT SENSE2 ISENSE2 VSENSE2 INPUT1 CS_DIS OUTPUT1 CURRENT SENSE1 OUTPUT2 IOUT1 VOUT1 ISENSE1 VSENSE1 IOUT2 VOUT2 VCC IGND Note: VFn = VOUTn - VCC during reverse battery condition. 2.1 Absolute maximum ratings Stressing the device above the rating listed in the "Absolute maximum ratings" table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to the conditions in table below for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality document. Table 3. Symbol VCC -VCC -IGND IOUT -IOUT IIN ICSD DC supply voltage Reverse DC supply voltage DC reverse ground pin current DC output current Reverse DC output current DC input current DC current sense disable input current Absolute maximum ratings Parameter Value 41 0.3 200 Internally limited 12 -1 to 10 -1 to 10 200 VCC-41 +VCC 104 Unit V V mA A A mA mA mA V V mJ -ICSENSE DC reverse CS pin current VCSENSE Current sense maximum voltage EMAX Maximum switching energy (L= 3mH; RL=0; Vbat=13.5V; Tjstart=150C; IOUT = IlimL(Typ.)) 7/38 Electrical specifications Table 3. Symbol VND5050AJ-E / VND5050AK-E Absolute maximum ratings (continued) Parameter Electrostatic discharge (Human Body Model: R=1.5K; C=100pF) - INPUT - CURRENT SENSE - CS_DIS - OUTPUT - VCC Charge device model (CDM-AEC-Q100-011) Junction operating temperature Storage temperature Value Unit VESD 4000 2000 4000 5000 5000 750 -40 to 150 -55 to 150 V V V V V V C C VESD Tj Tstg 2.2 Thermal data Table 4. Symbol Thermal data Value Parameter PowerSSO-12 PowerSSO-24 2.7 See Figure 33 C/W C/W Thermal resistance junction-case (Max.) (with one channel ON) Thermal resistance junction-ambient (Max.) Unit Rthj-case Rthj-amb 2.7 See Figure 29 8/38 VND5050AJ-E / VND5050AK-E Electrical specifications 2.3 Electrical characteristics 8V RON Vclamp IS Supply current 2(1) 3 5(1) 6 A mA IL(off) Off state output current(2) 0.01 3 5 0.7 A VF Output - VCC diode voltage (2) V 1. PowerMOS leakage included. 2. For each channel. Table 6. Symbol td(on) td(off) Switching (VCC = 13V; Tj = 25C) Parameter Turn-On delay time Turn-Off delay time Test conditions RL= 6.5 (see Figure 8) RL= 6.5 (see Figure 8) RL= 6.5 RL= 6.5 RL= 6.5 (see Figure 8) RL= 6.5 (see Figure 8) Min. Typ. 25 35 See Figure 21 See Figure 22 0.24 0.2 Max. Unit s s V/ s V/ s mJ mJ dVOUT/dt(on) Turn-On voltage slope dVOUT/dt(off) Turn-Off voltage slope WON WOFF Switching energy losses during twon Switching energy losses during twoff 9/38 Electrical specifications Table 7. Symbol VIL IIL VIH IIH VI(hyst) VICL VCSDL ICSDL VCSDH ICSDH VCSD(hyst) VCSCL VND5050AJ-E / VND5050AK-E Logic input Parameter Input low level voltage Low level input current Input high level voltage High level input current Input hysteresis voltage Input clamp voltage CS_DIS low level voltage Low level CS_DIS current CS_DIS high level voltage High level CS_DIS current CS_DIS hysteresis voltage CS_DIS clamp voltage ICSD= 1mA ICSD= -1mA VCSD= 2.1V 0.25 5.5 -0.7 7 VCSD= 0.9V 1 2.1 10 IIN= 1mA IIN= -1mA VIN= 2.1V 0.25 5.5 -0.7 0.9 7 VIN= 0.9V 1 2.1 10 Test conditions Min. Typ. Max. 0.9 Unit V A V A V V V V A V A V V V Table 8. Symbol IlimH IlimL TTSD TR TRS THYST VDEMAG Protections and diagnostics (1) Parameter DC short circuit current Short circuit current during thermal cycling Shutdown temperature Reset temperature Thermal reset of STATUS Thermal hysteresis (TTSD-TR) Turn-off output voltage clamp Output voltage drop limitation IOUT=2A; VIN=0; L=6mH IOUT=0.1A; Tj= -40C...+150C (see Figure 9) Test conditions VCC= 13V 5V TRS + 1 TRS + 5 135 VON 25 mV 1. To ensure long term reliability under heavy overload or short circuit conditions, protection and related diagnostic signals must be used together with a proper software strategy. If the device is subjected to abnormal conditions, this software must limit the duration and number of activation cycles. 10/38 VND5050AJ-E / VND5050AK-E Table 9. Symbol Electrical specifications Current sense (8V K0 IOUT/ISENSE 1270 2360 3450 K1 IOUT/ISENSE 1470 1570 -7 2020 2020 2610 2470 +7 % dK1/K1(1) IOUT=1A; VSENSE= 0.5V; Current sense ratio VCSD=0V; drift TJ=-40 C to 150 C IOUT/ISENSE IOUT=2A; VSENSE=4V;VCSD=0V; Tj= -40C Tj= 25C...150C K2 1740 1790 -4 2020 2020 2320 2250 +4 % dK2/K2 (1) IOUT=2 A; VSENSE= 4 V; Current sense ratio VCSD=0V; drift TJ=-40 C to 150 C IOUT/ISENSE IOUT=4A; VSENSE=4V;VCSD=0V; Tj=-40C Tj=25C...150C K3 1880 1900 -2 2010 2010 2160 2120 +2 % dK3/K3(1) IOUT=4 A; VSENSE= 4 V; Current sense ratio VCSD=0V; drift TJ=-40 C to 150 C IOUT=0A; VSENSE=0V; VCSD=5V; VIN=0V; Tj=-40C...150C 0 1 A ISENSE0 Analog sense leakage current VCSD=0V; VIN=5V; Tj=-40C...150C IOUT=2A; VSENSE=0V; VCSD=5V; VIN=5V; Tj=-40C...150C 0 2 A 0 4 1 20 A mA IOL Openload ON state current detection threshold Max analog sense output voltage Analog sense output voltage in overtemperature condition VIN = 5V, ISENSE= 5 A VSENSE IOUT=4A; VCSD=0V 5 V VSENSEH VCC=13V; RSENSE=10K 9 V 11/38 Electrical specifications Table 9. Symbol VND5050AJ-E / VND5050AK-E Current sense (8V ISENSEH VCC=13V; VSENSE=5V 8 mA Delay response time from falling tDSENSE1H edge of CS_DIS pin Delay response time from rising tDSENSE1L edge of CS_DIS pin Delay response tDSENSE2H time from rising edge of INPUT pin Delay response time between rising edge of output tDSENSE2H current and rising edge of current sense Delay response tDSENSE2L time from falling edge of INPUT pin VSENSE<4V, 0.5A 100 s 5 20 s 80 250 s 65 s 100 250 s 1. Parameter guaranteed by design; it is not tested. Figure 4. Current sense delay characteristics INPUT CS_DIS LOAD CURRENT SENSE CURRENT tDSENSE2H tDSENSE1L tDSENSE1H tDSENSE2L 12/38 VND5050AJ-E / VND5050AK-E Figure 5. Electrical specifications Delay response time between rising edge of ouput current and rising edge of current sense (CS enabled) VIN tDSENSE2H t IOUT IOUTMAX 90% IOUTMAX t ISENSE ISENSEMAX 90% ISENSEMAX t 13/38 Electrical specifications Figure 6. IOUT/ISENSE Vs. IOUT IOUT/ISENSE 3000 VND5050AJ-E / VND5050AK-E 2500 M ax -40 to 1 C C 50 M ax 25 to 150 C C 2000 M in 25 to 150 C C M in -40 to 1 C C 50 Typ 25 C 1500 1000 500 1 2 3 IOUT (A) 4 5 Figure 7. Maximum current sense ratio drift vs load current dk/k(%) 10 5 0 -5 -10 1 2 IOUT (A) 3 4 Note: Parameter guaranteed by design; it is not tested. 14/38 VND5050AJ-E / VND5050AK-E Table 10. Truth table Input L H L H L H L H H L H L Output L H L L L L L L L H H L Electrical specifications Conditions Normal operation Overtemperature Undervoltage Short circuit to GND (Rsc 10 m) Short circuit to VCC Negative output voltage clamp Sense (VCSD=0V)(1) 0 Nominal 0 VSENSEH 0 0 0 0 if Tj < TTSD VSENSEH if Tj > TTSD 0 < Nominal 0 1. If the VCSD is high, the SENSE output is at a high impedance, its potential depends on leakage currents and external circuit. Figure 8. Switching characteristics VOUT tWon 80% tWoff 90% dVOUT/dt(off) dVOUT/dt(on) tr 10% tf t INPUT td(on) td(off) t Figure 9. Output voltage drop limitation Vcc-Vout Tj=150oC Tj=25oC Tj=-40oC Von Iout Von/Ron(T) 15/38 Electrical specifications Table 11. ISO 7637-2: 2004(E) Test pulse 1 2a 3a 3b 4 5b (2) ISO 7637-2: 2004(E) Test pulse 1 2a 3a 3b 4 5b (2) III C C C C C C VND5050AJ-E / VND5050AK-E Electrical transient requirements Test levels (1) III -75V +37V -100V +75V -6V +65V IV -100V +50V -150V +100V -7V +87V Number of pulses or test times 5000 pulses 5000 pulses 1h 1h 1 pulse 1 pulse Test level results(1) IV C C C C C C Burst cycle/pulse repetition time 0.5 s 0.2 s 90 ms 90 ms 5s 5s 100 ms 100 ms Delays and impedance 2 ms, 10 50 s, 2 0.1 s, 50 0.1 s, 50 100 ms, 0.01 400 ms, 2 1. The above test levels must be considered referred to VCC = 13.5V except for pulse 5b. 2. Valid in case of external load dump clamp: 40V maximum referred to ground. Class C E Contents All functions of the device are performed as designed after exposure to disturbance. One or more functions of the device are not performed as designed after exposure to disturbance and cannot be returned to proper operation without replacing the device. 16/38 VND5050AJ-E / VND5050AK-E Figure 10. Waveforms NORMAL OPERATION INPUT CS_DIS LOAD CURRENT SENSE CURRENT UNDERVOLTAGE VCC INPUT CS_DIS LOAD CURRENT SENSE CURRENT VUSDhyst VUSD Electrical specifications SHORT TO VCC INPUT CS_DIS LOAD VOLTAGE LOAD CURRENT SENSE CURRENT ILIMH ILIML VSENSEH TR TTSD TRS current power limitation limitation thermal cycling SHORTED LOAD NORMAL LOAD 17/38 Electrical specifications VND5050AJ-E / VND5050AK-E 2.4 Electrical characteristics curves Figure 12. High level input current Iih (uA) 5 4.5 Figure 11. Off state output current Iloff (uA) 1 0.875 0.75 0.625 0.5 0.375 0.25 Off State Vcc= 13V Vin= Vout= 0V 4 3.5 3 2.5 2 1.5 1 Vin= 2.1V 0.125 0 -50 -25 0 25 50 75 100 125 150 175 0.5 0 -50 -25 0 25 50 75 100 125 150 175 Tc (C ) Tc (C ) Figure 13. Input clamp voltage Vicl (V) 7 6.8 6.6 6.4 6.2 6 5.8 5.6 5.4 5.2 5 -50 -25 0 25 50 75 100 125 150 175 Figure 14. Input high level Vih (V) 4 3.5 3 2.5 2 1.5 1 0.5 0 -50 -25 0 25 50 75 100 125 150 175 I 1mA in= Tc (C ) Tc (C ) Figure 15. Input low level Vil (V) 2 1.8 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 0 -50 -25 0 25 50 75 100 125 150 175 Figure 16. Input hysteresis voltage Vhyst (V) 1 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 -50 -25 0 25 50 75 100 125 150 175 Tc (C ) Tc (C ) 18/38 VND5050AJ-E / VND5050AK-E Electrical specifications Figure 17. On state resistance Vs. Tcase R on (mOhm) 100 90 80 70 60 50 40 30 20 10 0 -50 -25 0 25 50 75 100 125 150 175 Figure 18. On state resistance Vs. VCC R on (mOhm) 100 90 I out= 2A Vcc= 13V 80 70 60 50 40 30 20 10 0 0 5 10 15 20 25 Tc= 150C Tc= 125C Tc= 25C Tc= - 40C 30 35 40 Tc (C ) Vcc (V) Figure 19. Undervoltage shutdown Vusd (V) 16 14 12 10 8 6 4 2 0 -50 -25 0 25 50 75 100 125 150 175 Figure 20. ILIMH Vs. Tcase Ilimh (A) 25 22.5 Vcc=13V 20 17.5 15 12.5 10 7.5 5 -50 -25 0 25 50 75 100 125 150 175 Tc (C ) Tc (C ) Figure 21. Turn-On voltage slope (dVout/dt)on (V/ms) 1000 900 800 700 600 500 400 300 200 100 0 -50 -25 0 25 50 75 100 125 150 175 Figure 22. Turn-Off voltage slope (dVout/dt)off (V/ms) 1000 900 Vcc= 13V RI 6.5Ohm = 800 700 600 500 400 300 200 100 0 -50 -25 Vcc= 13V RI 6.5Ohm = 0 25 50 75 100 125 150 175 Tc (C ) Tc (C ) 19/38 Electrical specifications VND5050AJ-E / VND5050AK-E Figure 23. STAT_DIS clamp voltage Vsdcl(V) 14 Figure 24. Low level STAT_DIS voltage Vsdl(V) 8 7 12 I sd= 1mA 10 8 6 4 2 0 -50 -25 0 25 50 75 100 125 150 175 6 5 4 3 2 1 0 -50 -25 0 25 50 75 100 125 150 175 Tc (C ) Tc (C ) Figure 25. High level STAT_DIS voltage Vsdh(V) 8 7 6 5 4 3 2 1 0 -50 -25 0 25 50 75 100 125 150 175 Tc (C ) 20/38 VND5050AJ-E / VND5050AK-E Application information 3 Application information Figure 26. Application schematic +5V VCC Rprot CS_DIS Dld C Rprot INPUT OUTPUT Rprot CURRENT SENSE GND RSENSE CEXT VGND RGND DGND Note: Channel 2 has the same internal circuit as channel 1. 3.1 3.1.1 GND protection network against reverse battery Solution 1 : resistor in the ground line (RGND only) This can be used with any type of load. The following is an indication on how to dimension the RGND resistor. 1. 2. RGND 600mV / (IS(on)max). RGND (- CC) / (-IGND) V where -IGND is the DC reverse ground pin current and can be found in the absolute maximum rating section of the device datasheet. Power Dissipation in RGND (when VCC<0: during reverse battery situations) is: PD= (-VCC)2/RGND This resistor can be shared amongst several different HSDs. Please note that the value of this resistor should be calculated with formula (1) where IS(on)max becomes the sum of the maximum on-state currents of the different devices. Please note that if the microprocessor ground is not shared by the device ground then the RGND will produce a shift (IS(on)max * RGND) in the input thresholds and the status output values. This shift will vary depending on how many devices are ON in the case of several high side drivers sharing the same RGND. 21/38 Application information VND5050AJ-E / VND5050AK-E If the calculated power dissipation leads to a large resistor or several devices have to share the same resistor then ST suggests to utilize Solution 2 (see below). 3.1.2 Solution 2 : diode (DGND) in the ground line A resistor (RGND=1k) should be inserted in parallel to DGND if the device drives an inductive load. This small signal diode can be safely shared amongst several different HSDs. Also in this case, the presence of the ground network will produce a shift ( 600mV) in the input threshold and in the status output values if the microprocessor ground is not common to the device ground. This shift will not vary if more than one HSD shares the same diode/resistor network. 3.2 Load dump protection Dld is necessary (Voltage Transient Suppressor) if the load dump peak voltage exceeds the VCC max DC rating. The same applies if the device is subject to transients on the VCC line that are greater than the ones shown in the ISO 7637-2: 2004(E) table. 3.3 MCU I/Os protection If a ground protection network is used and negative transient are present on the VCC line, the control pins will be pulled negative. ST suggests to insert a resistor (Rprot) in line to prevent the C I/Os pins to latch-up. The value of these resistors is a compromise between the leakage current of C and the current required by the HSD I/Os (Input levels compatibility) with the latch-up limit of C I/Os. -VCCpeak/Ilatchup Rprot (VOHC-VIH-VGND) / IIHmax Calculation example: For VCCpeak= - 100V and Ilatchup 20mA; VOHC 4.5V 5k Rprot 180k . Recommended values: Rprot =10k CEXT=10nF. , 22/38 VND5050AJ-E / VND5050AK-E Application information 3.4 Maximum demagnetization energy (VCC = 13.5V) Figure 27. Maximum turn Off current versus inductance (for each channel) 100 A B 10 C I (A) 1 0,1 1 L (mH) 10 100 A: Tjstart = 150C single pulse B: Tjstart = 100C repetitive pulse C: Tjstart = 125C repetitive pulse VIN, IL Demagnetization Demagnetization Demagnetization t Note: Values are generated with RL =0 .In case of repetitive pulses, Tjstart (at beginning of each demagnetization) of every pulse must not exceed the temperature specified above for curves A and B. 23/38 Package and PCB thermal data VND5050AJ-E / VND5050AK-E 4 4.1 Package and PCB thermal data PowerSSO-12TM thermal data Figure 28. PowerSSO-12TM PC board Note: Layout condition of Rth and Zth measurements (PCB: Double layer, Thermal Vias, FR4 area= 77mm x 86mm,PCB thickness=1.6mm, Cu thickness=70m (front and back side), Copper areas: from minimum pad lay-out to 8cm2). Figure 29. Rthj-amb Vs. PCB copper area in open box free air condition (one channel ON) RTHj_amb(C/W) 70 65 60 55 50 45 40 35 30 0 2 4 6 8 10 PCB Cu heatsink area (cm^2) 24/38 VND5050AJ-E / VND5050AK-E Package and PCB thermal data Figure 30. PowerSSO-12TM thermal impedance junction ambient single pulse (one channel ON) ZTH (C/W) 100 Footprint 2 cm2 8 cm2 10 1 0,1 0,0001 0,001 0,01 0,1 1 Time (s) 10 100 1000 Equation 1: pulse calculation formula Z =R +Z ( 1 - ) TH TH THtp where = tP/T Figure 31. Thermal fitting model of a double channel HSD in PowerSSO-12TM (a) a. The fitting model is a semplified thermal tool and is valid for transient evolutions where the embedded protections (power limitation or thermal cycling during thermal shutdown) are not triggered. 25/38 Package and PCB thermal data Table 12. PowerSSO-12TM thermal parameter Footprint 0.7 2.8 4 8 22 26 0.001 0.0025 0.05 0.2 0.27 3 VND5050AJ-E / VND5050AK-E Area/island (cm2) R1= R7 (C/W) R2= R8 (C/W) R3 (C/W) R4 (C/W) R5 (C/W) R6 (C/W) C1= C7 (W.s/C) C2= C8 (W.s/C) C3 (W.s/C) C4 (W.s/C) C5 (W.s/C) C6 (W.s/C) 2 8 8 15 20 7 10 15 0.1 0.8 6 0.1 1 9 26/38 VND5050AJ-E / VND5050AK-E Package and PCB thermal data 4.2 PowerSSO-24TM thermal data Figure 32. PowerSSO-24TM PC board Note: Layout condition of Rth and Zth measurements (PCB: Double layer, Thermal Vias, FR4 area= 77mm x 86mm, PCB thickness=1.6mm, Cu thickness=70m (front and back side), Copper areas: from minimum pad lay-out to 8cm2). Figure 33. Rthj-amb Vs. PCB copper area in open box free air condition (one channel ON) RTHj_amb(C/ W) 55 50 45 40 35 30 0 2 4 6 8 10 PCB Cu heatsink area (cm^ 2) 27/38 Package and PCB thermal data VND5050AJ-E / VND5050AK-E Figure 34. PowerSSO-24TM Thermal impedance junction ambient single pulse (one channel ON) Equation 2: pulse calculation formula Z TH =R TH +Z THtp ( 1 - ) where = tP/T Figure 35. Thermal fitting model of a double channel HSD in PowerSSO-24TM(b) b. The fitting model is a semplified thermal tool and is valid for transient evolutions where the embedded protections (power limitation or thermal cycling during thermal shutdown) are not triggered. 28/38 VND5050AJ-E / VND5050AK-E Table 13. PowerSSO-24TM thermal parameter Footprint 0.4 2 6 7.7 9 28 0.001 0.0022 0.025 0.75 1 2.2 Package and PCB thermal data Area/island (cm2) R1=R7 (C/W) R2=R8 (C/W) R3 (C/W) R4 (C/W) R5 (C/W) R6 (C/W) C1=C7 (W.s/C) C2=C8 (W.s/C) C3 (W.s/C) C4 (W.s/C) C5 (W.s/C) C6 (W.s/C) 2 8 9 17 8 10 4 5 9 17 29/38 Package and packing information VND5050AJ-E / VND5050AK-E 5 5.1 Package and packing information ECOPACK(R) packages In order to meet environmental requirements, ST offers these devices in ECOPACK(R) packages. These packages have a Lead-free second-level interconnect. The category of Second-Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. 5.2 PowerSSO-12TM package information Figure 36. PowerSSO-12TM package dimensions 30/38 VND5050AJ-E / VND5050AK-E Table 14. PowerSSO-12TM mechanical data Package and packing information Millimeters Symbol Min. A A1 A2 B C D E e H h L k X Y ddd 5.8 0.25 0.4 0 1.9 3.6 1.25 0 1.10 0.23 0.19 4.8 3.8 0.8 6.2 0.5 1.27 8 2.5 4.2 0.1 Typ. Max. 1.62 0.1 1.65 0.41 0.25 5.0 4.0 31/38 Package and packing information VND5050AJ-E / VND5050AK-E 5.3 PowerSSO-24TM package information Figure 37. PowerSSO-24TM package dimensions Table 15. PowerSSO-24TM mechanical data Millimeters Symbol Min. A A2 a1 b c D E e e3 G G1 2.15 2.15 0 0.33 0.23 10.10 7.4 0.8 8.8 0.1 0.06 Typ. Max. 2.47 2.40 0.075 0.51 0.32 10.50 7.6 32/38 VND5050AJ-E / VND5050AK-E Table 15. Package and packing information PowerSSO-24TM mechanical data (continued) Millimeters Symbol Min. H h L N X Y 4.1 6.5 0.55 10.1 Typ. Max. 10.5 0.4 0.85 10deg 4.7 7.1 33/38 Package and packing information VND5050AJ-E / VND5050AK-E 5.4 PowerSSO-12TM packing information Figure 38. PowerSSO-12TM tube shipment (no suffix) B C A Base Q.ty Bulk Q.ty Tube length ( 0.5) A B C ( 0.1) All dimensions are in mm. 100 2000 532 1.85 6.75 0.6 Figure 39. PowerSSO-12TM tape and reel shipment (suffix "TR") REEL DIMENSIONS Base Q.ty Bulk Q.ty A (max) B (min) C ( 0.2) F G (+ 2 / -0) N (min) T (max) 2500 2500 330 1.5 13 20.2 12.4 60 18.4 TAPE DIMENSIONS According to Electronic Industries Association (EIA) Standard 481 rev. A, Feb. 1986 Tape width Tape Hole Spacing Component Spacing Hole Diameter Hole Diameter Hole Position Compartment Depth Hole Spacing All dimensions are in mm. End W P0 ( 0.1) P D ( 0.05) D1 (min) F ( 0.1) K (max) P1 ( 0.1) 12 4 8 1.5 1.5 5.5 4.5 2 Start Top cover tape No components 500mm min Empty components pockets saled with cover tape. User direction of feed 500mm min Components No components 34/38 VND5050AJ-E / VND5050AK-E Package and packing information 5.5 PowerSSO-24TM packing information Figure 40. PowerSS0-24TM tube shipment (no suffix) C B Base Qty Bulk Qty Tube length (0.5) A B C (0.1) All dimensions are in mm. 49 1225 532 3.5 13.8 0.6 A Figure 41. PowerSSO-24TM tape and reel shipment (suffix "TR") REEL DIMENSIONS Base Qty Bulk Qty A (max) B (min) C ( 0.2) F G (+2 / -0) N (min) T (max) 1000 1000 330 1.5 13 20.2 24.4 100 30.4 TAPE DIMENSIONS According to Electronic Industries Association (EIA) Standard 481 rev. A, Feb. 1986 Tape width Tape Hole Spacing Component Spacing Hole Diameter Hole Diameter Hole Position Compartment Depth Hole Spacing All dimensions are in mm. Start Top cover tape No components Components 500mm min No components W P0 ( 0.1) P D ( 0.05) D1 (min) F ( 0.1) K (max) P1 ( 0.1) 24 4 12 1.55 1.5 11.5 2.85 2 End 500mm min Empty components pockets sealed with cover tape. User direction of feed 35/38 Order codes VND5050AJ-E / VND5050AK-E 6 Order codes Table 16. Device summary Order codes Package Part number (Tube) PowerSSO-12 PowerSSO-24 VND5050AJ-E VND5050AK-E Part number (Tape & Reel) VND5050AJTR-E VND5050AKTR-E 36/38 VND5050AJ-E / VND5050AK-E Revision history 7 Revision history Table 17. Date 30-Mar-2006 14-Apr-2006 26-Apr-2007 Document revision history Revision 1 2 3 Initial release. PowerSSO-24 dimensions table update. Reformatted Figure 31 title corrected Table 3 : corrected EMAX value. Table 9 : added dk1/k1, dk2/k2, dk3/k3, tDSENSE2H . Added Figure 5. Updated Figure 6. Added Figure 7. Table 11 : Updated test level values III and IV for test pulse 5b and notes. Added Section 3.4: Maximum demagnetization energy (VCC = 13.5V). Figure 31: Thermal fitting model of a double channel HSD in PowerSSO-12TM, Figure 35: Thermal fitting model of a double channel HSD in PowerSSO-24TM: added notes. Updated Table 9: Current sense (8V 4 01-Jun-2007 5 4-Dec-2007 6 12-Feb-2008 7 37/38 VND5050AJ-E / VND5050AK-E Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries ("ST") reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST's terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such third party products or services or any intellectual property contained therein. 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Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any liability of ST. ST and the ST logo are trademarks or registered trademarks of ST in various countries. Information in this document supersedes and replaces all information previously supplied. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners. (c) 2008 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com 38/38 |
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